  //CPM-XPIPE wires
  wire phy_rdy;
  wire xpipe_gt_rxusrclk;
  wire xpipe_gt_rxoutclk;
  wire xpipe_phyready_fr_bot;
  wire xpipe_phyready_to_bot;

  wire gt_refclk0_div2_ibuf;
  wire gt_refclk1_div2_ibuf;
  
  wire xpipe_lnk0_bufgtce;
  wire xpipe_lnk1_bufgtce;
  wire xpipe_lnk0_bufgtrst;
  wire xpipe_lnk1_bufgtrst;
  wire xpipe_lnk0_phy_ready;
  wire xpipe_lnk1_phy_ready;
  wire xpipe_lnk1_gt_outclk;
  wire xpipe_lnk0_gt_outclk;
  wire xpipe_lnk0_gt_pipeclk;
  wire xpipe_lnk1_gt_pipeclk;
  wire xpipe_lnk0_pcie_perst_n;
  wire xpipe_lnk1_pcie_perst_n;
  wire xpipe_lnk0_phyesmadaptsave;
  wire xpipe_lnk1_phyesmadaptsave;
  wire xpipe_lnk0_pcielinkreachtarget;
  wire xpipe_lnk1_pcielinkreachtarget;

  wire[11:0] xpipe_lnk0_bufgtdiv;
  wire[11:0] xpipe_lnk1_bufgtdiv;
  wire [2:0] xpipe_lnk0_pcie_rate;
  wire [2:0] xpipe_lnk1_pcie_rate;
  wire [3:0] xpipe_lnk0_bufgtce_mask;
  wire [3:0] xpipe_lnk1_bufgtce_mask;
  wire [3:0] xpipe_lnk0_bufgtrst_mask;
  wire [3:0] xpipe_lnk1_bufgtrst_mask;
  wire [5:0] xpipe_lnk0_pcieltssmstate;
  wire [5:0] xpipe_lnk1_pcieltssmstate;

  wire q0q1_xpipe_bufgtce_m;
  wire q1q2_xpipe_bufgtce_m;
  wire q2q3_xpipe_bufgtce_m;
  wire q0q1_xpipe_bufgtrst_m;
  wire q1q2_xpipe_bufgtrst_m;
  wire q2q3_xpipe_bufgtrst_m;
  wire q0q1_xpipe_bufgtce_m_1;
  wire q0q1_xpipe_gt_outclk_m;
  wire q0q1_xpipe_phy_ready_m;
  wire q1q2_xpipe_bufgtce_m_1;
  wire q1q2_xpipe_gt_outclk_m;
  wire q1q2_xpipe_phy_ready_m;
  wire q2q3_xpipe_bufgtce_m_1;
  wire q2q3_xpipe_gt_outclk_m;
  wire q2q3_xpipe_phy_ready_m;
  wire q0q1_xpipe_bufgtrst_m_1;
  wire q0q1_xpipe_gt_pipeclk_m;
  wire q1q2_xpipe_bufgtrst_m_1;
  wire q1q2_xpipe_gt_pipeclk_m;
  wire q2q3_xpipe_bufgtrst_m_1;
  wire q2q3_xpipe_gt_pipeclk_m;
  wire q0q1_xpipe_gt_outclk_m_1;
  wire q0q1_xpipe_gt_rxoutclk_m;
  wire q0q1_xpipe_gt_rxusrclk_m;
  wire q0q1_xpipe_phy_ready_m_1;
  wire q1q2_xpipe_gt_outclk_m_1;
  wire q1q2_xpipe_gt_rxoutclk_m;
  wire q1q2_xpipe_gt_rxusrclk_m;
  wire q1q2_xpipe_phy_ready_m_1;
  wire q2q3_xpipe_gt_outclk_m_1;
  wire q2q3_xpipe_gt_rxoutclk_m;
  wire q2q3_xpipe_gt_rxusrclk_m;
  wire q2q3_xpipe_phy_ready_m_1;
  wire q0q1_xpipe_gt_pipeclk_m_1;
  wire q0q1_xpipe_pcie_perst_n_m;
  wire q1q2_xpipe_gt_pipeclk_m_1;
  wire q1q2_xpipe_pcie_perst_n_m;
  wire q2q3_xpipe_gt_pipeclk_m_1;
  wire q2q3_xpipe_pcie_perst_n_m;
  wire q0q1_xpipe_pcie_perst_n_m_1;
  wire q1q2_xpipe_pcie_perst_n_m_1;
  wire q2q3_xpipe_pcie_perst_n_m_1;
  wire q0q1_xpipe_phyesmadaptsave_m;
  wire q0q1_xpipe_phyready_fr_bot_m;
  wire q0q1_xpipe_phyready_to_bot_m;
  wire q1q2_xpipe_phyesmadaptsave_m;
  wire q1q2_xpipe_phyready_fr_bot_m;
  wire q1q2_xpipe_phyready_to_bot_m;
  wire q2q3_xpipe_phyesmadaptsave_m;
  wire q2q3_xpipe_phyready_fr_bot_m;
  wire q2q3_xpipe_phyready_to_bot_m;
  wire q3q4_xpipe_phyesmadaptsave_m;
  wire q0q1_xpipe_phyesmadaptsave_m_1;
  wire q1q2_xpipe_phyesmadaptsave_m_1;
  wire q2q3_xpipe_phyesmadaptsave_m_1;
  wire q3q4_xpipe_phyesmadaptsave_m_1;
  wire q0q1_xpipe_pcielinkreachtarget_m;
  wire q1q2_xpipe_pcielinkreachtarget_m;
  wire q2q3_xpipe_pcielinkreachtarget_m;
  wire q0q1_xpipe_pcielinkreachtarget_m_1;
  wire q1q2_xpipe_pcielinkreachtarget_m_1;
  wire q2q3_xpipe_pcielinkreachtarget_m_1;

  wire[11:0] q0q1_xpipe_bufgtdiv_m;
  wire[11:0] q1q2_xpipe_bufgtdiv_m;
  wire[11:0] q2q3_xpipe_bufgtdiv_m;
  wire[11:0] q0q1_xpipe_bufgtdiv_m_1;
  wire[11:0] q1q2_xpipe_bufgtdiv_m_1;
  wire[11:0] q2q3_xpipe_bufgtdiv_m_1;
  wire [3:0] q0q1_xpipe_bufgtce_mask_m;
  wire [3:0] q1q2_xpipe_bufgtce_mask_m;
  wire [3:0] q2q3_xpipe_bufgtce_mask_m;
  wire [3:0] q0q1_xpipe_bufgtrst_mask_m;
  wire [3:0] q1q2_xpipe_bufgtrst_mask_m;
  wire [3:0] q2q3_xpipe_bufgtrst_mask_m;
  wire [3:0] q0q1_xpipe_bufgtce_mask_m_1;
  wire [3:0] q1q2_xpipe_bufgtce_mask_m_1;
  wire [3:0] q2q3_xpipe_bufgtce_mask_m_1;
  wire [3:0] q0q1_xpipe_bufgtrst_mask_m_1;
  wire [3:0] q1q2_xpipe_bufgtrst_mask_m_1;
  wire [3:0] q2q3_xpipe_bufgtrst_mask_m_1;

  wire hsdp_xpipe_ch0_rxpcsreset;
  wire hsdp_xpipe_ch1_rxpcsreset;
  wire hsdp_xpipe_ch2_rxpcsreset;
  wire hsdp_xpipe_ch0_rxdatavalid;
  wire hsdp_xpipe_ch0_rxresetdone;
  wire hsdp_xpipe_ch0_txresetdone;
  wire hsdp_xpipe_ch1_rxdatavalid;
  wire hsdp_xpipe_ch1_rxresetdone;
  wire hsdp_xpipe_ch1_txresetdone;
  wire hsdp_xpipe_ch2_rxdatavalid;
  wire hsdp_xpipe_ch2_rxresetdone;
  wire hsdp_xpipe_ch2_txresetdone;
  wire hsdp_xpipe_ch0_rxgearboxslip;
  wire hsdp_xpipe_ch0_rxheadervalid;
  wire hsdp_xpipe_ch1_rxgearboxslip;
  wire hsdp_xpipe_ch1_rxheadervalid;
  wire hsdp_xpipe_ch2_rxgearboxslip;
  wire hsdp_xpipe_ch2_rxheadervalid;

  wire [1:0] hsdp_xpipe_ch0_rxheader;
  wire [1:0] hsdp_xpipe_ch0_txheader;
  wire [1:0] hsdp_xpipe_ch1_rxheader;
  wire [1:0] hsdp_xpipe_ch1_txheader;
  wire [1:0] hsdp_xpipe_ch2_rxheader;
  wire [1:0] hsdp_xpipe_ch2_txheader;
  wire [6:0] hsdp_xpipe_ch0_txsequence;
  wire [6:0] hsdp_xpipe_ch1_txsequence;
  wire [6:0] hsdp_xpipe_ch2_txsequence;

  wire q0q1_hsdp_xpipe_ch0_rxpcsreset;
  wire q0q1_hsdp_xpipe_ch1_rxpcsreset;
  wire q0q1_hsdp_xpipe_ch2_rxpcsreset;
  wire q1q2_hsdp_xpipe_ch0_rxpcsreset;
  wire q1q2_hsdp_xpipe_ch1_rxpcsreset;
  wire q1q2_hsdp_xpipe_ch2_rxpcsreset;
  wire q2q3_hsdp_xpipe_ch0_rxpcsreset;
  wire q2q3_hsdp_xpipe_ch1_rxpcsreset;
  wire q2q3_hsdp_xpipe_ch2_rxpcsreset;
  wire q0q1_hsdp_xpipe_ch0_rxdatavalid;
  wire q0q1_hsdp_xpipe_ch0_rxresetdone;
  wire q0q1_hsdp_xpipe_ch0_txresetdone;
  wire q0q1_hsdp_xpipe_ch1_rxdatavalid;
  wire q0q1_hsdp_xpipe_ch1_rxresetdone;
  wire q0q1_hsdp_xpipe_ch1_txresetdone;
  wire q0q1_hsdp_xpipe_ch2_rxdatavalid;
  wire q0q1_hsdp_xpipe_ch2_rxresetdone;
  wire q0q1_hsdp_xpipe_ch2_txresetdone;
  wire q1q2_hsdp_xpipe_ch0_rxdatavalid;
  wire q1q2_hsdp_xpipe_ch0_rxresetdone;
  wire q1q2_hsdp_xpipe_ch0_txresetdone;
  wire q1q2_hsdp_xpipe_ch1_rxdatavalid;
  wire q1q2_hsdp_xpipe_ch1_rxresetdone;
  wire q1q2_hsdp_xpipe_ch1_txresetdone;
  wire q1q2_hsdp_xpipe_ch2_rxdatavalid;
  wire q1q2_hsdp_xpipe_ch2_rxresetdone;
  wire q1q2_hsdp_xpipe_ch2_txresetdone;
  wire q2q3_hsdp_xpipe_ch0_rxdatavalid;
  wire q2q3_hsdp_xpipe_ch0_rxresetdone;
  wire q2q3_hsdp_xpipe_ch0_txresetdone;
  wire q2q3_hsdp_xpipe_ch1_rxdatavalid;
  wire q2q3_hsdp_xpipe_ch1_rxresetdone;
  wire q2q3_hsdp_xpipe_ch1_txresetdone;
  wire q2q3_hsdp_xpipe_ch2_rxdatavalid;
  wire q2q3_hsdp_xpipe_ch2_rxresetdone;
  wire q2q3_hsdp_xpipe_ch2_txresetdone;
  wire q0q1_hsdp_xpipe_ch0_rxgearboxslip;
  wire q0q1_hsdp_xpipe_ch0_rxheadervalid;
  wire q0q1_hsdp_xpipe_ch1_rxgearboxslip;
  wire q0q1_hsdp_xpipe_ch1_rxheadervalid;
  wire q0q1_hsdp_xpipe_ch2_rxgearboxslip;
  wire q0q1_hsdp_xpipe_ch2_rxheadervalid;
  wire q1q2_hsdp_xpipe_ch0_rxgearboxslip;
  wire q1q2_hsdp_xpipe_ch0_rxheadervalid;
  wire q1q2_hsdp_xpipe_ch1_rxgearboxslip;
  wire q1q2_hsdp_xpipe_ch1_rxheadervalid;
  wire q1q2_hsdp_xpipe_ch2_rxgearboxslip;
  wire q1q2_hsdp_xpipe_ch2_rxheadervalid;
  wire q2q3_hsdp_xpipe_ch0_rxgearboxslip;
  wire q2q3_hsdp_xpipe_ch0_rxheadervalid;
  wire q2q3_hsdp_xpipe_ch1_rxgearboxslip;
  wire q2q3_hsdp_xpipe_ch1_rxheadervalid;
  wire q2q3_hsdp_xpipe_ch2_rxgearboxslip;
  wire q2q3_hsdp_xpipe_ch2_rxheadervalid;

  wire [1:0] q0q1_hsdp_xpipe_ch0_rxheader;
  wire [1:0] q0q1_hsdp_xpipe_ch0_txheader;
  wire [1:0] q0q1_hsdp_xpipe_ch1_rxheader;
  wire [1:0] q0q1_hsdp_xpipe_ch1_txheader;
  wire [1:0] q0q1_hsdp_xpipe_ch2_rxheader;
  wire [1:0] q0q1_hsdp_xpipe_ch2_txheader;
  wire [1:0] q1q2_hsdp_xpipe_ch0_rxheader;
  wire [1:0] q1q2_hsdp_xpipe_ch0_txheader;
  wire [1:0] q1q2_hsdp_xpipe_ch1_rxheader;
  wire [1:0] q1q2_hsdp_xpipe_ch1_txheader;
  wire [1:0] q1q2_hsdp_xpipe_ch2_rxheader;
  wire [1:0] q1q2_hsdp_xpipe_ch2_txheader;
  wire [1:0] q2q3_hsdp_xpipe_ch0_rxheader;
  wire [1:0] q2q3_hsdp_xpipe_ch0_txheader;
  wire [1:0] q2q3_hsdp_xpipe_ch1_rxheader;
  wire [1:0] q2q3_hsdp_xpipe_ch1_txheader;
  wire [1:0] q2q3_hsdp_xpipe_ch2_rxheader;
  wire [1:0] q2q3_hsdp_xpipe_ch2_txheader;
  wire [6:0] q0q1_hsdp_xpipe_ch0_txsequence;
  wire [6:0] q0q1_hsdp_xpipe_ch1_txsequence;
  wire [6:0] q0q1_hsdp_xpipe_ch2_txsequence;
  wire [6:0] q1q2_hsdp_xpipe_ch0_txsequence;
  wire [6:0] q1q2_hsdp_xpipe_ch1_txsequence;
  wire [6:0] q1q2_hsdp_xpipe_ch2_txsequence;
  wire [6:0] q2q3_hsdp_xpipe_ch0_txsequence;
  wire [6:0] q2q3_hsdp_xpipe_ch1_txsequence;
  wire [6:0] q2q3_hsdp_xpipe_ch2_txsequence;

  wire xpipe_rxmarginresreq_0;
  wire xpipe_rxmarginresreq_1;
  wire xpipe_rxmarginresreq_2;
  wire xpipe_rxmarginresreq_3;
  wire xpipe_rxmarginreqreq_0;
  wire xpipe_rxmarginreqreq_1;
  wire xpipe_rxmarginreqreq_2;
  wire xpipe_rxmarginreqreq_3;
  wire xpipe_rxmarginresack_0;
  wire xpipe_rxmarginresack_1;
  wire xpipe_rxmarginresack_2;
  wire xpipe_rxmarginresack_3;
  wire xpipe_rxmarginreqack_0;
  wire xpipe_rxmarginreqack_1;
  wire xpipe_rxmarginreqack_2;
  wire xpipe_rxmarginreqack_3;

  wire [3:0] xpipe_rxmarginrescmd_0;
  wire [3:0] xpipe_rxmarginrescmd_1;
  wire [3:0] xpipe_rxmarginrescmd_2;
  wire [3:0] xpipe_rxmarginrescmd_3;
  wire [3:0] xpipe_rxmarginreqcmd_0;
  wire [3:0] xpipe_rxmarginreqcmd_1;
  wire [3:0] xpipe_rxmarginreqcmd_2;
  wire [3:0] xpipe_rxmarginreqcmd_3;
  wire [1:0] xpipe_rxmarginreslanenum_0;
  wire [1:0] xpipe_rxmarginreslanenum_1;
  wire [1:0] xpipe_rxmarginreslanenum_2;
  wire [1:0] xpipe_rxmarginreslanenum_3;
  wire [7:0] xpipe_rxmarginrespayload_0;
  wire [7:0] xpipe_rxmarginrespayload_1;
  wire [7:0] xpipe_rxmarginrespayload_2;
  wire [7:0] xpipe_rxmarginrespayload_3;
  wire [1:0] xpipe_rxmarginreqlanenum_0;
  wire [1:0] xpipe_rxmarginreqlanenum_1;
  wire [1:0] xpipe_rxmarginreqlanenum_2;
  wire [1:0] xpipe_rxmarginreqlanenum_3;
  wire [7:0] xpipe_rxmarginreqpayload_0;
  wire [7:0] xpipe_rxmarginreqpayload_1;
  wire [7:0] xpipe_rxmarginreqpayload_2;
  wire [7:0] xpipe_rxmarginreqpayload_3;

  wire q0q1_xpipe_rxmarginreqack_m;
  wire q0q1_xpipe_rxmarginreqreq_m;
  wire q0q1_xpipe_rxmarginresack_m;
  wire q0q1_xpipe_rxmarginresreq_m;
  wire q1q2_xpipe_rxmarginreqack_m;
  wire q1q2_xpipe_rxmarginreqreq_m;
  wire q1q2_xpipe_rxmarginresack_m;
  wire q1q2_xpipe_rxmarginresreq_m;
  wire q2q3_xpipe_rxmarginreqack_m;
  wire q2q3_xpipe_rxmarginreqreq_m;
  wire q2q3_xpipe_rxmarginresack_m;
  wire q2q3_xpipe_rxmarginresreq_m;
  wire q0q1_xpipe_rxmarginreqack_m_1;
  wire q0q1_xpipe_rxmarginreqack_m_2;
  wire q0q1_xpipe_rxmarginreqack_m_3;
  wire q0q1_xpipe_rxmarginreqreq_m_1;
  wire q0q1_xpipe_rxmarginreqreq_m_2;
  wire q0q1_xpipe_rxmarginreqreq_m_3;
  wire q0q1_xpipe_rxmarginresack_m_1;
  wire q0q1_xpipe_rxmarginresack_m_2;
  wire q0q1_xpipe_rxmarginresack_m_3;
  wire q0q1_xpipe_rxmarginresreq_m_1;
  wire q0q1_xpipe_rxmarginresreq_m_2;
  wire q0q1_xpipe_rxmarginresreq_m_3;
  wire q1q2_xpipe_rxmarginreqack_m_1;
  wire q1q2_xpipe_rxmarginreqack_m_2;
  wire q1q2_xpipe_rxmarginreqack_m_3;
  wire q1q2_xpipe_rxmarginreqreq_m_1;
  wire q1q2_xpipe_rxmarginreqreq_m_2;
  wire q1q2_xpipe_rxmarginreqreq_m_3;
  wire q1q2_xpipe_rxmarginresack_m_1;
  wire q1q2_xpipe_rxmarginresack_m_2;
  wire q1q2_xpipe_rxmarginresack_m_3;
  wire q1q2_xpipe_rxmarginresreq_m_1;
  wire q1q2_xpipe_rxmarginresreq_m_2;
  wire q1q2_xpipe_rxmarginresreq_m_3;
  wire q2q3_xpipe_rxmarginreqack_m_1;
  wire q2q3_xpipe_rxmarginreqack_m_2;
  wire q2q3_xpipe_rxmarginreqack_m_3;
  wire q2q3_xpipe_rxmarginreqreq_m_1;
  wire q2q3_xpipe_rxmarginreqreq_m_2;
  wire q2q3_xpipe_rxmarginreqreq_m_3;
  wire q2q3_xpipe_rxmarginresack_m_1;
  wire q2q3_xpipe_rxmarginresack_m_2;
  wire q2q3_xpipe_rxmarginresack_m_3;
  wire q2q3_xpipe_rxmarginresreq_m_1;
  wire q2q3_xpipe_rxmarginresreq_m_2;
  wire q2q3_xpipe_rxmarginresreq_m_3;
  
  wire [2:0] q0q1_xpipe_pcie_rate_m;
  wire [2:0] q1q2_xpipe_pcie_rate_m;
  wire [2:0] q2q3_xpipe_pcie_rate_m;
  wire [2:0] q0q1_xpipe_pcie_rate_m_1;
  wire [2:0] q1q2_xpipe_pcie_rate_m_1;
  wire [2:0] q2q3_xpipe_pcie_rate_m_1;
  wire [3:0] q0q1_xpipe_rxmarginreqcmd_m;
  wire [3:0] q0q1_xpipe_rxmarginrescmd_m;
  wire [3:0] q1q2_xpipe_rxmarginreqcmd_m;
  wire [3:0] q1q2_xpipe_rxmarginrescmd_m;
  wire [3:0] q2q3_xpipe_rxmarginreqcmd_m;
  wire [3:0] q2q3_xpipe_rxmarginrescmd_m;
  wire [5:0] q0q1_xpipe_pcieltssmstate_m;
  wire [5:0] q1q2_xpipe_pcieltssmstate_m;
  wire [5:0] q2q3_xpipe_pcieltssmstate_m;
  wire [3:0] q0q1_xpipe_rxmarginreqcmd_m_1;
  wire [3:0] q0q1_xpipe_rxmarginreqcmd_m_2;
  wire [3:0] q0q1_xpipe_rxmarginreqcmd_m_3;
  wire [3:0] q0q1_xpipe_rxmarginrescmd_m_1;
  wire [3:0] q0q1_xpipe_rxmarginrescmd_m_2;
  wire [3:0] q0q1_xpipe_rxmarginrescmd_m_3;
  wire [3:0] q1q2_xpipe_rxmarginreqcmd_m_1;
  wire [3:0] q1q2_xpipe_rxmarginreqcmd_m_2;
  wire [3:0] q1q2_xpipe_rxmarginreqcmd_m_3;
  wire [3:0] q1q2_xpipe_rxmarginrescmd_m_1;
  wire [3:0] q1q2_xpipe_rxmarginrescmd_m_2;
  wire [3:0] q1q2_xpipe_rxmarginrescmd_m_3;
  wire [3:0] q2q3_xpipe_rxmarginreqcmd_m_1;
  wire [3:0] q2q3_xpipe_rxmarginreqcmd_m_2;
  wire [3:0] q2q3_xpipe_rxmarginreqcmd_m_3;
  wire [3:0] q2q3_xpipe_rxmarginrescmd_m_1;
  wire [3:0] q2q3_xpipe_rxmarginrescmd_m_2;
  wire [3:0] q2q3_xpipe_rxmarginrescmd_m_3;
  wire [5:0] q0q1_xpipe_pcieltssmstate_m_1;
  wire [5:0] q1q2_xpipe_pcieltssmstate_m_1;
  wire [5:0] q2q3_xpipe_pcieltssmstate_m_1;
  wire [1:0] q0q1_xpipe_rxmarginreqlanenum_m;
  wire [1:0] q0q1_xpipe_rxmarginreslanenum_m;
  wire [1:0] q1q2_xpipe_rxmarginreqlanenum_m;
  wire [1:0] q1q2_xpipe_rxmarginreslanenum_m;
  wire [1:0] q2q3_xpipe_rxmarginreqlanenum_m;
  wire [1:0] q2q3_xpipe_rxmarginreslanenum_m;
  wire [7:0] q0q1_xpipe_rxmarginreqpayload_m;
  wire [7:0] q0q1_xpipe_rxmarginrespayload_m;
  wire [7:0] q1q2_xpipe_rxmarginreqpayload_m;
  wire [7:0] q1q2_xpipe_rxmarginrespayload_m;
  wire [7:0] q2q3_xpipe_rxmarginreqpayload_m;
  wire [7:0] q2q3_xpipe_rxmarginrespayload_m;
  wire [1:0] q0q1_xpipe_rxmarginreqlanenum_m_1;
  wire [1:0] q0q1_xpipe_rxmarginreqlanenum_m_2;
  wire [1:0] q0q1_xpipe_rxmarginreqlanenum_m_3;
  wire [1:0] q0q1_xpipe_rxmarginreslanenum_m_1;
  wire [1:0] q0q1_xpipe_rxmarginreslanenum_m_2;
  wire [1:0] q0q1_xpipe_rxmarginreslanenum_m_3;
  wire [1:0] q1q2_xpipe_rxmarginreqlanenum_m_1;
  wire [1:0] q1q2_xpipe_rxmarginreqlanenum_m_2;
  wire [1:0] q1q2_xpipe_rxmarginreqlanenum_m_3;
  wire [1:0] q1q2_xpipe_rxmarginreslanenum_m_1;
  wire [1:0] q1q2_xpipe_rxmarginreslanenum_m_2;
  wire [1:0] q1q2_xpipe_rxmarginreslanenum_m_3;
  wire [1:0] q2q3_xpipe_rxmarginreqlanenum_m_1;
  wire [1:0] q2q3_xpipe_rxmarginreqlanenum_m_2;
  wire [1:0] q2q3_xpipe_rxmarginreqlanenum_m_3;
  wire [1:0] q2q3_xpipe_rxmarginreslanenum_m_1;
  wire [1:0] q2q3_xpipe_rxmarginreslanenum_m_2;
  wire [1:0] q2q3_xpipe_rxmarginreslanenum_m_3;
  wire [7:0] q0q1_xpipe_rxmarginreqpayload_m_1;
  wire [7:0] q0q1_xpipe_rxmarginreqpayload_m_2;
  wire [7:0] q0q1_xpipe_rxmarginreqpayload_m_3;
  wire [7:0] q0q1_xpipe_rxmarginrespayload_m_1;
  wire [7:0] q0q1_xpipe_rxmarginrespayload_m_2;
  wire [7:0] q0q1_xpipe_rxmarginrespayload_m_3;
  wire [7:0] q1q2_xpipe_rxmarginreqpayload_m_1;
  wire [7:0] q1q2_xpipe_rxmarginreqpayload_m_2;
  wire [7:0] q1q2_xpipe_rxmarginreqpayload_m_3;
  wire [7:0] q1q2_xpipe_rxmarginrespayload_m_1;
  wire [7:0] q1q2_xpipe_rxmarginrespayload_m_2;
  wire [7:0] q1q2_xpipe_rxmarginrespayload_m_3;
  wire [7:0] q2q3_xpipe_rxmarginreqpayload_m_1;
  wire [7:0] q2q3_xpipe_rxmarginreqpayload_m_2;
  wire [7:0] q2q3_xpipe_rxmarginreqpayload_m_3;
  wire [7:0] q2q3_xpipe_rxmarginrespayload_m_1;
  wire [7:0] q2q3_xpipe_rxmarginrespayload_m_2;
  wire [7:0] q2q3_xpipe_rxmarginrespayload_m_3;


  wire        cpm_xpipe_ch0_phystatus;
  wire [1:0]  cpm_xpipe_ch0_powerdown;
  wire [1:0]  cpm_xpipe_ch0_rxcharisk;
  wire [31:0] cpm_xpipe_ch0_rxdata;
  wire        cpm_xpipe_ch0_rxdatavalid;
  wire        cpm_xpipe_ch0_rxelecidle;
  wire        cpm_xpipe_ch0_rxpolarity;
  wire        cpm_xpipe_ch0_rxstartblock;
  wire [2:0]  cpm_xpipe_ch0_rxstatus;
  wire [1:0]  cpm_xpipe_ch0_rxsyncheader;
  wire        cpm_xpipe_ch0_rxtermination;
  wire        cpm_xpipe_ch0_rxvalid;
  wire [1:0]  cpm_xpipe_ch0_txcharisk;
  wire        cpm_xpipe_ch0_txcompliance;
  wire [31:0] cpm_xpipe_ch0_txdata;
  wire        cpm_xpipe_ch0_txdatavalid;
  wire        cpm_xpipe_ch0_txdeemph;
  wire        cpm_xpipe_ch0_txdetectrxloopback;
  wire        cpm_xpipe_ch0_txelecidle;
  wire [6:0]  cpm_xpipe_ch0_txmaincursor;
  wire [2:0]  cpm_xpipe_ch0_txmargin;
  wire [4:0]  cpm_xpipe_ch0_txpostcursor;
  wire [4:0]  cpm_xpipe_ch0_txprecursor;
  wire        cpm_xpipe_ch0_txstartblock;
  wire        cpm_xpipe_ch0_txswing;
  wire [1:0]  cpm_xpipe_ch0_txsyncheader;

  wire        cpm_xpipe_ch1_phystatus;
  wire [1:0]  cpm_xpipe_ch1_powerdown;
  wire [1:0]  cpm_xpipe_ch1_rxcharisk;
  wire [31:0] cpm_xpipe_ch1_rxdata;
  wire        cpm_xpipe_ch1_rxdatavalid;
  wire        cpm_xpipe_ch1_rxelecidle;
  wire        cpm_xpipe_ch1_rxpolarity;
  wire        cpm_xpipe_ch1_rxstartblock;
  wire [2:0]  cpm_xpipe_ch1_rxstatus;
  wire [1:0]  cpm_xpipe_ch1_rxsyncheader;
  wire        cpm_xpipe_ch1_rxtermination;
  wire        cpm_xpipe_ch1_rxvalid;
  wire [1:0]  cpm_xpipe_ch1_txcharisk;
  wire        cpm_xpipe_ch1_txcompliance;
  wire [31:0] cpm_xpipe_ch1_txdata;
  wire        cpm_xpipe_ch1_txdatavalid;
  wire        cpm_xpipe_ch1_txdeemph;
  wire        cpm_xpipe_ch1_txdetectrxloopback;
  wire        cpm_xpipe_ch1_txelecidle;
  wire [6:0]  cpm_xpipe_ch1_txmaincursor;
  wire [2:0]  cpm_xpipe_ch1_txmargin;
  wire [4:0]  cpm_xpipe_ch1_txpostcursor;
  wire [4:0]  cpm_xpipe_ch1_txprecursor;
  wire        cpm_xpipe_ch1_txstartblock;
  wire        cpm_xpipe_ch1_txswing;
  wire [1:0]  cpm_xpipe_ch1_txsyncheader;

  wire        cpm_xpipe_ch2_phystatus;
  wire [1:0]  cpm_xpipe_ch2_powerdown;
  wire [1:0]  cpm_xpipe_ch2_rxcharisk;
  wire [31:0] cpm_xpipe_ch2_rxdata;
  wire        cpm_xpipe_ch2_rxdatavalid;
  wire        cpm_xpipe_ch2_rxelecidle;
  wire        cpm_xpipe_ch2_rxpolarity;
  wire        cpm_xpipe_ch2_rxstartblock;
  wire [2:0]  cpm_xpipe_ch2_rxstatus;
  wire [1:0]  cpm_xpipe_ch2_rxsyncheader;
  wire        cpm_xpipe_ch2_rxtermination;
  wire        cpm_xpipe_ch2_rxvalid;
  wire [1:0]  cpm_xpipe_ch2_txcharisk;
  wire        cpm_xpipe_ch2_txcompliance;
  wire [31:0] cpm_xpipe_ch2_txdata;
  wire        cpm_xpipe_ch2_txdatavalid;
  wire        cpm_xpipe_ch2_txdeemph;
  wire        cpm_xpipe_ch2_txdetectrxloopback;
  wire        cpm_xpipe_ch2_txelecidle;
  wire [6:0]  cpm_xpipe_ch2_txmaincursor;
  wire [2:0]  cpm_xpipe_ch2_txmargin;
  wire [4:0]  cpm_xpipe_ch2_txpostcursor;
  wire [4:0]  cpm_xpipe_ch2_txprecursor;
  wire        cpm_xpipe_ch2_txstartblock;
  wire        cpm_xpipe_ch2_txswing;
  wire [1:0]  cpm_xpipe_ch2_txsyncheader;

  wire        cpm_xpipe_ch3_phystatus;
  wire [1:0]  cpm_xpipe_ch3_powerdown;
  wire [1:0]  cpm_xpipe_ch3_rxcharisk;
  wire [31:0] cpm_xpipe_ch3_rxdata;
  wire        cpm_xpipe_ch3_rxdatavalid;
  wire        cpm_xpipe_ch3_rxelecidle;
  wire        cpm_xpipe_ch3_rxpolarity;
  wire        cpm_xpipe_ch3_rxstartblock;
  wire [2:0]  cpm_xpipe_ch3_rxstatus;
  wire [1:0]  cpm_xpipe_ch3_rxsyncheader;
  wire        cpm_xpipe_ch3_rxtermination;
  wire        cpm_xpipe_ch3_rxvalid;
  wire [1:0]  cpm_xpipe_ch3_txcharisk;
  wire        cpm_xpipe_ch3_txcompliance;
  wire [31:0] cpm_xpipe_ch3_txdata;
  wire        cpm_xpipe_ch3_txdatavalid;
  wire        cpm_xpipe_ch3_txdeemph;
  wire        cpm_xpipe_ch3_txdetectrxloopback;
  wire        cpm_xpipe_ch3_txelecidle;
  wire [6:0]  cpm_xpipe_ch3_txmaincursor;
  wire [2:0]  cpm_xpipe_ch3_txmargin;
  wire [4:0]  cpm_xpipe_ch3_txpostcursor;
  wire [4:0]  cpm_xpipe_ch3_txprecursor;
  wire        cpm_xpipe_ch3_txstartblock;
  wire        cpm_xpipe_ch3_txswing;
  wire [1:0]  cpm_xpipe_ch3_txsyncheader;

  wire        cpm_xpipe_ch4_phystatus;
  wire [1:0]  cpm_xpipe_ch4_powerdown;
  wire [1:0]  cpm_xpipe_ch4_rxcharisk;
  wire [31:0] cpm_xpipe_ch4_rxdata;
  wire        cpm_xpipe_ch4_rxdatavalid;
  wire        cpm_xpipe_ch4_rxelecidle;
  wire        cpm_xpipe_ch4_rxpolarity;
  wire        cpm_xpipe_ch4_rxstartblock;
  wire [2:0]  cpm_xpipe_ch4_rxstatus;
  wire [1:0]  cpm_xpipe_ch4_rxsyncheader;
  wire        cpm_xpipe_ch4_rxtermination;
  wire        cpm_xpipe_ch4_rxvalid;
  wire [1:0]  cpm_xpipe_ch4_txcharisk;
  wire        cpm_xpipe_ch4_txcompliance;
  wire [31:0] cpm_xpipe_ch4_txdata;
  wire        cpm_xpipe_ch4_txdatavalid;
  wire        cpm_xpipe_ch4_txdeemph;
  wire        cpm_xpipe_ch4_txdetectrxloopback;
  wire        cpm_xpipe_ch4_txelecidle;
  wire [6:0]  cpm_xpipe_ch4_txmaincursor;
  wire [2:0]  cpm_xpipe_ch4_txmargin;
  wire [4:0]  cpm_xpipe_ch4_txpostcursor;
  wire [4:0]  cpm_xpipe_ch4_txprecursor;
  wire        cpm_xpipe_ch4_txstartblock;
  wire        cpm_xpipe_ch4_txswing;
  wire [1:0]  cpm_xpipe_ch4_txsyncheader;

  wire        cpm_xpipe_ch5_phystatus;
  wire [1:0]  cpm_xpipe_ch5_powerdown;
  wire [1:0]  cpm_xpipe_ch5_rxcharisk;
  wire [31:0] cpm_xpipe_ch5_rxdata;
  wire        cpm_xpipe_ch5_rxdatavalid;
  wire        cpm_xpipe_ch5_rxelecidle;
  wire        cpm_xpipe_ch5_rxpolarity;
  wire        cpm_xpipe_ch5_rxstartblock;
  wire [2:0]  cpm_xpipe_ch5_rxstatus;
  wire [1:0]  cpm_xpipe_ch5_rxsyncheader;
  wire        cpm_xpipe_ch5_rxtermination;
  wire        cpm_xpipe_ch5_rxvalid;
  wire [1:0]  cpm_xpipe_ch5_txcharisk;
  wire        cpm_xpipe_ch5_txcompliance;
  wire [31:0] cpm_xpipe_ch5_txdata;
  wire        cpm_xpipe_ch5_txdatavalid;
  wire        cpm_xpipe_ch5_txdeemph;
  wire        cpm_xpipe_ch5_txdetectrxloopback;
  wire        cpm_xpipe_ch5_txelecidle;
  wire [6:0]  cpm_xpipe_ch5_txmaincursor;
  wire [2:0]  cpm_xpipe_ch5_txmargin;
  wire [4:0]  cpm_xpipe_ch5_txpostcursor;
  wire [4:0]  cpm_xpipe_ch5_txprecursor;
  wire        cpm_xpipe_ch5_txstartblock;
  wire        cpm_xpipe_ch5_txswing;
  wire [1:0]  cpm_xpipe_ch5_txsyncheader;

  wire        cpm_xpipe_ch6_phystatus;
  wire [1:0]  cpm_xpipe_ch6_powerdown;
  wire [1:0]  cpm_xpipe_ch6_rxcharisk;
  wire [31:0] cpm_xpipe_ch6_rxdata;
  wire        cpm_xpipe_ch6_rxdatavalid;
  wire        cpm_xpipe_ch6_rxelecidle;
  wire        cpm_xpipe_ch6_rxpolarity;
  wire        cpm_xpipe_ch6_rxstartblock;
  wire [2:0]  cpm_xpipe_ch6_rxstatus;
  wire [1:0]  cpm_xpipe_ch6_rxsyncheader;
  wire        cpm_xpipe_ch6_rxtermination;
  wire        cpm_xpipe_ch6_rxvalid;
  wire [1:0]  cpm_xpipe_ch6_txcharisk;
  wire        cpm_xpipe_ch6_txcompliance;
  wire [31:0] cpm_xpipe_ch6_txdata;
  wire        cpm_xpipe_ch6_txdatavalid;
  wire        cpm_xpipe_ch6_txdeemph;
  wire        cpm_xpipe_ch6_txdetectrxloopback;
  wire        cpm_xpipe_ch6_txelecidle;
  wire [6:0]  cpm_xpipe_ch6_txmaincursor;
  wire [2:0]  cpm_xpipe_ch6_txmargin;
  wire [4:0]  cpm_xpipe_ch6_txpostcursor;
  wire [4:0]  cpm_xpipe_ch6_txprecursor;
  wire        cpm_xpipe_ch6_txstartblock;
  wire        cpm_xpipe_ch6_txswing;
  wire [1:0]  cpm_xpipe_ch6_txsyncheader;

  wire        cpm_xpipe_ch7_phystatus;
  wire [1:0]  cpm_xpipe_ch7_powerdown;
  wire [1:0]  cpm_xpipe_ch7_rxcharisk;
  wire [31:0] cpm_xpipe_ch7_rxdata;
  wire        cpm_xpipe_ch7_rxdatavalid;
  wire        cpm_xpipe_ch7_rxelecidle;
  wire        cpm_xpipe_ch7_rxpolarity;
  wire        cpm_xpipe_ch7_rxstartblock;
  wire [2:0]  cpm_xpipe_ch7_rxstatus;
  wire [1:0]  cpm_xpipe_ch7_rxsyncheader;
  wire        cpm_xpipe_ch7_rxtermination;
  wire        cpm_xpipe_ch7_rxvalid;
  wire [1:0]  cpm_xpipe_ch7_txcharisk;
  wire        cpm_xpipe_ch7_txcompliance;
  wire [31:0] cpm_xpipe_ch7_txdata;
  wire        cpm_xpipe_ch7_txdatavalid;
  wire        cpm_xpipe_ch7_txdeemph;
  wire        cpm_xpipe_ch7_txdetectrxloopback;
  wire        cpm_xpipe_ch7_txelecidle;
  wire [6:0]  cpm_xpipe_ch7_txmaincursor;
  wire [2:0]  cpm_xpipe_ch7_txmargin;
  wire [4:0]  cpm_xpipe_ch7_txpostcursor;
  wire [4:0]  cpm_xpipe_ch7_txprecursor;
  wire        cpm_xpipe_ch7_txstartblock;
  wire        cpm_xpipe_ch7_txswing;
  wire [1:0]  cpm_xpipe_ch7_txsyncheader;

  wire        cpm_xpipe_ch8_phystatus;
  wire [1:0]  cpm_xpipe_ch8_powerdown;
  wire [1:0]  cpm_xpipe_ch8_rxcharisk;
  wire [31:0] cpm_xpipe_ch8_rxdata;
  wire        cpm_xpipe_ch8_rxdatavalid;
  wire        cpm_xpipe_ch8_rxelecidle;
  wire        cpm_xpipe_ch8_rxpolarity;
  wire        cpm_xpipe_ch8_rxstartblock;
  wire [2:0]  cpm_xpipe_ch8_rxstatus;
  wire [1:0]  cpm_xpipe_ch8_rxsyncheader;
  wire        cpm_xpipe_ch8_rxtermination;
  wire        cpm_xpipe_ch8_rxvalid;
  wire [1:0]  cpm_xpipe_ch8_txcharisk;
  wire        cpm_xpipe_ch8_txcompliance;
  wire [31:0] cpm_xpipe_ch8_txdata;
  wire        cpm_xpipe_ch8_txdatavalid;
  wire        cpm_xpipe_ch8_txdeemph;
  wire        cpm_xpipe_ch8_txdetectrxloopback;
  wire        cpm_xpipe_ch8_txelecidle;
  wire [6:0]  cpm_xpipe_ch8_txmaincursor;
  wire [2:0]  cpm_xpipe_ch8_txmargin;
  wire [4:0]  cpm_xpipe_ch8_txpostcursor;
  wire [4:0]  cpm_xpipe_ch8_txprecursor;
  wire        cpm_xpipe_ch8_txstartblock;
  wire        cpm_xpipe_ch8_txswing;
  wire [1:0]  cpm_xpipe_ch8_txsyncheader;

  wire        cpm_xpipe_ch9_phystatus;
  wire [1:0]  cpm_xpipe_ch9_powerdown;
  wire [1:0]  cpm_xpipe_ch9_rxcharisk;
  wire [31:0] cpm_xpipe_ch9_rxdata;
  wire        cpm_xpipe_ch9_rxdatavalid;
  wire        cpm_xpipe_ch9_rxelecidle;
  wire        cpm_xpipe_ch9_rxpolarity;
  wire        cpm_xpipe_ch9_rxstartblock;
  wire [2:0]  cpm_xpipe_ch9_rxstatus;
  wire [1:0]  cpm_xpipe_ch9_rxsyncheader;
  wire        cpm_xpipe_ch9_rxtermination;
  wire        cpm_xpipe_ch9_rxvalid;
  wire [1:0]  cpm_xpipe_ch9_txcharisk;
  wire        cpm_xpipe_ch9_txcompliance;
  wire [31:0] cpm_xpipe_ch9_txdata;
  wire        cpm_xpipe_ch9_txdatavalid;
  wire        cpm_xpipe_ch9_txdeemph;
  wire        cpm_xpipe_ch9_txdetectrxloopback;
  wire        cpm_xpipe_ch9_txelecidle;
  wire [6:0]  cpm_xpipe_ch9_txmaincursor;
  wire [2:0]  cpm_xpipe_ch9_txmargin;
  wire [4:0]  cpm_xpipe_ch9_txpostcursor;
  wire [4:0]  cpm_xpipe_ch9_txprecursor;
  wire        cpm_xpipe_ch9_txstartblock;
  wire        cpm_xpipe_ch9_txswing;
  wire [1:0]  cpm_xpipe_ch9_txsyncheader;

  wire        cpm_xpipe_ch10_phystatus;
  wire [1:0]  cpm_xpipe_ch10_powerdown;
  wire [1:0]  cpm_xpipe_ch10_rxcharisk;
  wire [31:0] cpm_xpipe_ch10_rxdata;
  wire        cpm_xpipe_ch10_rxdatavalid;
  wire        cpm_xpipe_ch10_rxelecidle;
  wire        cpm_xpipe_ch10_rxpolarity;
  wire        cpm_xpipe_ch10_rxstartblock;
  wire [2:0]  cpm_xpipe_ch10_rxstatus;
  wire [1:0]  cpm_xpipe_ch10_rxsyncheader;
  wire        cpm_xpipe_ch10_rxtermination;
  wire        cpm_xpipe_ch10_rxvalid;
  wire [1:0]  cpm_xpipe_ch10_txcharisk;
  wire        cpm_xpipe_ch10_txcompliance;
  wire [31:0] cpm_xpipe_ch10_txdata;
  wire        cpm_xpipe_ch10_txdatavalid;
  wire        cpm_xpipe_ch10_txdeemph;
  wire        cpm_xpipe_ch10_txdetectrxloopback;
  wire        cpm_xpipe_ch10_txelecidle;
  wire [6:0]  cpm_xpipe_ch10_txmaincursor;
  wire [2:0]  cpm_xpipe_ch10_txmargin;
  wire [4:0]  cpm_xpipe_ch10_txpostcursor;
  wire [4:0]  cpm_xpipe_ch10_txprecursor;
  wire        cpm_xpipe_ch10_txstartblock;
  wire        cpm_xpipe_ch10_txswing;
  wire [1:0]  cpm_xpipe_ch10_txsyncheader;

  wire        cpm_xpipe_ch11_phystatus;
  wire [1:0]  cpm_xpipe_ch11_powerdown;
  wire [1:0]  cpm_xpipe_ch11_rxcharisk;
  wire [31:0] cpm_xpipe_ch11_rxdata;
  wire        cpm_xpipe_ch11_rxdatavalid;
  wire        cpm_xpipe_ch11_rxelecidle;
  wire        cpm_xpipe_ch11_rxpolarity;
  wire        cpm_xpipe_ch11_rxstartblock;
  wire [2:0]  cpm_xpipe_ch11_rxstatus;
  wire [1:0]  cpm_xpipe_ch11_rxsyncheader;
  wire        cpm_xpipe_ch11_rxtermination;
  wire        cpm_xpipe_ch11_rxvalid;
  wire [1:0]  cpm_xpipe_ch11_txcharisk;
  wire        cpm_xpipe_ch11_txcompliance;
  wire [31:0] cpm_xpipe_ch11_txdata;
  wire        cpm_xpipe_ch11_txdatavalid;
  wire        cpm_xpipe_ch11_txdeemph;
  wire        cpm_xpipe_ch11_txdetectrxloopback;
  wire        cpm_xpipe_ch11_txelecidle;
  wire [6:0]  cpm_xpipe_ch11_txmaincursor;
  wire [2:0]  cpm_xpipe_ch11_txmargin;
  wire [4:0]  cpm_xpipe_ch11_txpostcursor;
  wire [4:0]  cpm_xpipe_ch11_txprecursor;
  wire        cpm_xpipe_ch11_txstartblock;
  wire        cpm_xpipe_ch11_txswing;
  wire [1:0]  cpm_xpipe_ch11_txsyncheader;

  wire        cpm_xpipe_ch12_phystatus;
  wire [1:0]  cpm_xpipe_ch12_powerdown;
  wire [1:0]  cpm_xpipe_ch12_rxcharisk;
  wire [31:0] cpm_xpipe_ch12_rxdata;
  wire        cpm_xpipe_ch12_rxdatavalid;
  wire        cpm_xpipe_ch12_rxelecidle;
  wire        cpm_xpipe_ch12_rxpolarity;
  wire        cpm_xpipe_ch12_rxstartblock;
  wire [2:0]  cpm_xpipe_ch12_rxstatus;
  wire [1:0]  cpm_xpipe_ch12_rxsyncheader;
  wire        cpm_xpipe_ch12_rxtermination;
  wire        cpm_xpipe_ch12_rxvalid;
  wire [1:0]  cpm_xpipe_ch12_txcharisk;
  wire        cpm_xpipe_ch12_txcompliance;
  wire [31:0] cpm_xpipe_ch12_txdata;
  wire        cpm_xpipe_ch12_txdatavalid;
  wire        cpm_xpipe_ch12_txdeemph;
  wire        cpm_xpipe_ch12_txdetectrxloopback;
  wire        cpm_xpipe_ch12_txelecidle;
  wire [6:0]  cpm_xpipe_ch12_txmaincursor;
  wire [2:0]  cpm_xpipe_ch12_txmargin;
  wire [4:0]  cpm_xpipe_ch12_txpostcursor;
  wire [4:0]  cpm_xpipe_ch12_txprecursor;
  wire        cpm_xpipe_ch12_txstartblock;
  wire        cpm_xpipe_ch12_txswing;
  wire [1:0]  cpm_xpipe_ch12_txsyncheader;

  wire        cpm_xpipe_ch13_phystatus;
  wire [1:0]  cpm_xpipe_ch13_powerdown;
  wire [1:0]  cpm_xpipe_ch13_rxcharisk;
  wire [31:0] cpm_xpipe_ch13_rxdata;
  wire        cpm_xpipe_ch13_rxdatavalid;
  wire        cpm_xpipe_ch13_rxelecidle;
  wire        cpm_xpipe_ch13_rxpolarity;
  wire        cpm_xpipe_ch13_rxstartblock;
  wire [2:0]  cpm_xpipe_ch13_rxstatus;
  wire [1:0]  cpm_xpipe_ch13_rxsyncheader;
  wire        cpm_xpipe_ch13_rxtermination;
  wire        cpm_xpipe_ch13_rxvalid;
  wire [1:0]  cpm_xpipe_ch13_txcharisk;
  wire        cpm_xpipe_ch13_txcompliance;
  wire [31:0] cpm_xpipe_ch13_txdata;
  wire        cpm_xpipe_ch13_txdatavalid;
  wire        cpm_xpipe_ch13_txdeemph;
  wire        cpm_xpipe_ch13_txdetectrxloopback;
  wire        cpm_xpipe_ch13_txelecidle;
  wire [6:0]  cpm_xpipe_ch13_txmaincursor;
  wire [2:0]  cpm_xpipe_ch13_txmargin;
  wire [4:0]  cpm_xpipe_ch13_txpostcursor;
  wire [4:0]  cpm_xpipe_ch13_txprecursor;
  wire        cpm_xpipe_ch13_txstartblock;
  wire        cpm_xpipe_ch13_txswing;
  wire [1:0]  cpm_xpipe_ch13_txsyncheader;

  wire        cpm_xpipe_ch14_phystatus;
  wire [1:0]  cpm_xpipe_ch14_powerdown;
  wire [1:0]  cpm_xpipe_ch14_rxcharisk;
  wire [31:0] cpm_xpipe_ch14_rxdata;
  wire        cpm_xpipe_ch14_rxdatavalid;
  wire        cpm_xpipe_ch14_rxelecidle;
  wire        cpm_xpipe_ch14_rxpolarity;
  wire        cpm_xpipe_ch14_rxstartblock;
  wire [2:0]  cpm_xpipe_ch14_rxstatus;
  wire [1:0]  cpm_xpipe_ch14_rxsyncheader;
  wire        cpm_xpipe_ch14_rxtermination;
  wire        cpm_xpipe_ch14_rxvalid;
  wire [1:0]  cpm_xpipe_ch14_txcharisk;
  wire        cpm_xpipe_ch14_txcompliance;
  wire [31:0] cpm_xpipe_ch14_txdata;
  wire        cpm_xpipe_ch14_txdatavalid;
  wire        cpm_xpipe_ch14_txdeemph;
  wire        cpm_xpipe_ch14_txdetectrxloopback;
  wire        cpm_xpipe_ch14_txelecidle;
  wire [6:0]  cpm_xpipe_ch14_txmaincursor;
  wire [2:0]  cpm_xpipe_ch14_txmargin;
  wire [4:0]  cpm_xpipe_ch14_txpostcursor;
  wire [4:0]  cpm_xpipe_ch14_txprecursor;
  wire        cpm_xpipe_ch14_txstartblock;
  wire        cpm_xpipe_ch14_txswing;
  wire [1:0]  cpm_xpipe_ch14_txsyncheader;

  wire        cpm_xpipe_ch15_phystatus;
  wire [1:0]  cpm_xpipe_ch15_powerdown;
  wire [1:0]  cpm_xpipe_ch15_rxcharisk;
  wire [31:0] cpm_xpipe_ch15_rxdata;
  wire        cpm_xpipe_ch15_rxdatavalid;
  wire        cpm_xpipe_ch15_rxelecidle;
  wire        cpm_xpipe_ch15_rxpolarity;
  wire        cpm_xpipe_ch15_rxstartblock;
  wire [2:0]  cpm_xpipe_ch15_rxstatus;
  wire [1:0]  cpm_xpipe_ch15_rxsyncheader;
  wire        cpm_xpipe_ch15_rxtermination;
  wire        cpm_xpipe_ch15_rxvalid;
  wire [1:0]  cpm_xpipe_ch15_txcharisk;
  wire        cpm_xpipe_ch15_txcompliance;
  wire [31:0] cpm_xpipe_ch15_txdata;
  wire        cpm_xpipe_ch15_txdatavalid;
  wire        cpm_xpipe_ch15_txdeemph;
  wire        cpm_xpipe_ch15_txdetectrxloopback;
  wire        cpm_xpipe_ch15_txelecidle;
  wire [6:0]  cpm_xpipe_ch15_txmaincursor;
  wire [2:0]  cpm_xpipe_ch15_txmargin;
  wire [4:0]  cpm_xpipe_ch15_txpostcursor;
  wire [4:0]  cpm_xpipe_ch15_txprecursor;
  wire        cpm_xpipe_ch15_txstartblock;
  wire        cpm_xpipe_ch15_txswing;
  wire [1:0]  cpm_xpipe_ch15_txsyncheader;

  wire        q0q1_xpipe_pipe_ch0_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch0_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch0_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch0_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch0_rxdata_m;
  wire        q0q1_xpipe_pipe_ch0_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch0_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch0_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch0_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch0_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch0_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch0_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch0_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch0_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch0_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch0_txdata_m;
  wire        q0q1_xpipe_pipe_ch0_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch0_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch0_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch0_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch0_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch0_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch0_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch0_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch0_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch0_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch1_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch1_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch1_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch1_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch1_rxdata_m;
  wire        q0q1_xpipe_pipe_ch1_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch1_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch1_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch1_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch1_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch1_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch1_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch1_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch1_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch1_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch1_txdata_m;
  wire        q0q1_xpipe_pipe_ch1_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch1_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch1_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch1_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch1_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch1_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch1_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch1_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch1_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch1_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch2_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch2_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch2_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch2_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch2_rxdata_m;
  wire        q0q1_xpipe_pipe_ch2_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch2_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch2_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch2_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch2_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch2_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch2_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch2_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch2_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch2_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch2_txdata_m;
  wire        q0q1_xpipe_pipe_ch2_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch2_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch2_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch2_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch2_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch2_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch2_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch2_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch2_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch2_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch3_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch3_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch3_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch3_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch3_rxdata_m;
  wire        q0q1_xpipe_pipe_ch3_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch3_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch3_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch3_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch3_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch3_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch3_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch3_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch3_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch3_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch3_txdata_m;
  wire        q0q1_xpipe_pipe_ch3_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch3_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch3_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch3_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch3_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch3_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch3_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch3_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch3_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch3_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch4_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch4_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch4_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch4_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch4_rxdata_m;
  wire        q0q1_xpipe_pipe_ch4_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch4_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch4_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch4_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch4_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch4_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch4_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch4_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch4_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch4_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch4_txdata_m;
  wire        q0q1_xpipe_pipe_ch4_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch4_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch4_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch4_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch4_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch4_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch4_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch4_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch4_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch4_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch5_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch5_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch5_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch5_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch5_rxdata_m;
  wire        q0q1_xpipe_pipe_ch5_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch5_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch5_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch5_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch5_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch5_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch5_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch5_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch5_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch5_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch5_txdata_m;
  wire        q0q1_xpipe_pipe_ch5_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch5_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch5_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch5_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch5_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch5_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch5_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch5_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch5_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch5_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch6_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch6_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch6_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch6_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch6_rxdata_m;
  wire        q0q1_xpipe_pipe_ch6_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch6_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch6_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch6_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch6_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch6_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch6_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch6_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch6_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch6_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch6_txdata_m;
  wire        q0q1_xpipe_pipe_ch6_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch6_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch6_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch6_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch6_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch6_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch6_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch6_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch6_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch6_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch7_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch7_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch7_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch7_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch7_rxdata_m;
  wire        q0q1_xpipe_pipe_ch7_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch7_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch7_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch7_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch7_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch7_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch7_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch7_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch7_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch7_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch7_txdata_m;
  wire        q0q1_xpipe_pipe_ch7_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch7_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch7_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch7_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch7_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch7_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch7_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch7_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch7_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch7_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch8_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch8_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch8_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch8_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch8_rxdata_m;
  wire        q0q1_xpipe_pipe_ch8_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch8_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch8_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch8_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch8_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch8_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch8_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch8_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch8_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch8_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch8_txdata_m;
  wire        q0q1_xpipe_pipe_ch8_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch8_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch8_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch8_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch8_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch8_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch8_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch8_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch8_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch8_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch9_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch9_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch9_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch9_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch9_rxdata_m;
  wire        q0q1_xpipe_pipe_ch9_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch9_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch9_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch9_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch9_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch9_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch9_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch9_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch9_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch9_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch9_txdata_m;
  wire        q0q1_xpipe_pipe_ch9_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch9_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch9_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch9_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch9_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch9_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch9_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch9_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch9_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch9_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch10_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch10_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch10_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch10_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch10_rxdata_m;
  wire        q0q1_xpipe_pipe_ch10_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch10_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch10_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch10_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch10_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch10_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch10_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch10_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch10_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch10_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch10_txdata_m;
  wire        q0q1_xpipe_pipe_ch10_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch10_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch10_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch10_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch10_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch10_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch10_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch10_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch10_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch10_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch11_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch11_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch11_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch11_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch11_rxdata_m;
  wire        q0q1_xpipe_pipe_ch11_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch11_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch11_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch11_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch11_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch11_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch11_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch11_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch11_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch11_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch11_txdata_m;
  wire        q0q1_xpipe_pipe_ch11_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch11_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch11_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch11_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch11_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch11_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch11_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch11_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch11_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch11_txsyncheader_m;
  wire        q0q1_xpipe_pipe_ch12_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch12_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch12_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch12_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch12_rxdata_m;
  wire        q0q1_xpipe_pipe_ch12_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch12_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch12_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch12_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch12_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch12_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch12_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch12_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch12_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch12_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch12_txdata_m;
  wire        q0q1_xpipe_pipe_ch12_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch12_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch12_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch12_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch12_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch12_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch12_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch12_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch12_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch12_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch13_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch13_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch13_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch13_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch13_rxdata_m;
  wire        q0q1_xpipe_pipe_ch13_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch13_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch13_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch13_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch13_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch13_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch13_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch13_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch13_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch13_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch13_txdata_m;
  wire        q0q1_xpipe_pipe_ch13_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch13_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch13_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch13_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch13_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch13_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch13_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch13_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch13_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch13_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch14_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch14_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch14_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch14_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch14_rxdata_m;
  wire        q0q1_xpipe_pipe_ch14_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch14_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch14_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch14_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch14_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch14_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch14_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch14_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch14_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch14_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch14_txdata_m;
  wire        q0q1_xpipe_pipe_ch14_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch14_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch14_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch14_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch14_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch14_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch14_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch14_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch14_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch14_txsyncheader_m;

  wire        q0q1_xpipe_pipe_ch15_phystatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch15_powerdown_m;
  wire [1:0]  q0q1_xpipe_pipe_ch15_rxcharisk_m;
  wire        q0q1_xpipe_pipe_ch15_rxdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch15_rxdata_m;
  wire        q0q1_xpipe_pipe_ch15_rxelecidle_m;
  wire        q0q1_xpipe_pipe_ch15_rxpolarity_m;
  wire        q0q1_xpipe_pipe_ch15_rxstartblock_m;
  wire [2:0]  q0q1_xpipe_pipe_ch15_rxstatus_m;
  wire [1:0]  q0q1_xpipe_pipe_ch15_rxsyncheader_m;
  wire        q0q1_xpipe_pipe_ch15_rxtermination_m;
  wire        q0q1_xpipe_pipe_ch15_rxvalid_m;
  wire [1:0]  q0q1_xpipe_pipe_ch15_txcharisk_m;
  wire        q0q1_xpipe_pipe_ch15_txcompliance_m;
  wire        q0q1_xpipe_pipe_ch15_txdatavalid_m;
  wire [31:0] q0q1_xpipe_pipe_ch15_txdata_m;
  wire        q0q1_xpipe_pipe_ch15_txdeemph_m;
  wire        q0q1_xpipe_pipe_ch15_txdetectrxloopback_m;
  wire        q0q1_xpipe_pipe_ch15_txelecidle_m;
  wire [6:0]  q0q1_xpipe_pipe_ch15_txmaincursor_m;
  wire [2:0]  q0q1_xpipe_pipe_ch15_txmargin_m;
  wire [4:0]  q0q1_xpipe_pipe_ch15_txpostcursor_m;
  wire [4:0]  q0q1_xpipe_pipe_ch15_txprecursor_m;
  wire        q0q1_xpipe_pipe_ch15_txstartblock_m;
  wire        q0q1_xpipe_pipe_ch15_txswing_m;
  wire [1:0]  q0q1_xpipe_pipe_ch15_txsyncheader_m;

  wire [1:0]  q1q2_xpipe_pipe_ch0_powerdown_m;
  wire        q1q2_xpipe_pipe_ch0_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch0_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch0_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch0_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch0_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch0_txdata_m;
  wire        q1q2_xpipe_pipe_ch0_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch0_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch0_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch0_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch0_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch0_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch0_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch0_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch0_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch0_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch0_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch0_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch0_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch0_rxdata_m;
  wire        q1q2_xpipe_pipe_ch0_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch0_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch0_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch0_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch0_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch1_powerdown_m;
  wire        q1q2_xpipe_pipe_ch1_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch1_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch1_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch1_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch1_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch1_txdata_m;
  wire        q1q2_xpipe_pipe_ch1_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch1_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch1_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch1_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch1_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch1_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch1_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch1_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch1_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch1_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch1_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch1_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch1_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch1_rxdata_m;
  wire        q1q2_xpipe_pipe_ch1_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch1_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch1_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch1_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch1_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch2_powerdown_m;
  wire        q1q2_xpipe_pipe_ch2_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch2_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch2_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch2_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch2_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch2_txdata_m;
  wire        q1q2_xpipe_pipe_ch2_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch2_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch2_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch2_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch2_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch2_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch2_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch2_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch2_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch2_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch2_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch2_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch2_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch2_rxdata_m;
  wire        q1q2_xpipe_pipe_ch2_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch2_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch2_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch2_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch2_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch3_powerdown_m;
  wire        q1q2_xpipe_pipe_ch3_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch3_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch3_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch3_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch3_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch3_txdata_m;
  wire        q1q2_xpipe_pipe_ch3_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch3_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch3_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch3_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch3_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch3_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch3_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch3_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch3_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch3_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch3_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch3_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch3_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch3_rxdata_m;
  wire        q1q2_xpipe_pipe_ch3_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch3_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch3_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch3_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch3_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch4_powerdown_m;
  wire        q1q2_xpipe_pipe_ch4_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch4_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch4_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch4_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch4_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch4_txdata_m;
  wire        q1q2_xpipe_pipe_ch4_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch4_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch4_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch4_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch4_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch4_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch4_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch4_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch4_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch4_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch4_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch4_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch4_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch4_rxdata_m;
  wire        q1q2_xpipe_pipe_ch4_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch4_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch4_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch4_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch4_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch5_powerdown_m;
  wire        q1q2_xpipe_pipe_ch5_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch5_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch5_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch5_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch5_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch5_txdata_m;
  wire        q1q2_xpipe_pipe_ch5_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch5_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch5_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch5_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch5_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch5_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch5_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch5_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch5_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch5_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch5_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch5_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch5_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch5_rxdata_m;
  wire        q1q2_xpipe_pipe_ch5_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch5_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch5_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch5_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch5_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch6_powerdown_m;
  wire        q1q2_xpipe_pipe_ch6_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch6_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch6_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch6_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch6_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch6_txdata_m;
  wire        q1q2_xpipe_pipe_ch6_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch6_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch6_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch6_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch6_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch6_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch6_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch6_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch6_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch6_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch6_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch6_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch6_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch6_rxdata_m;
  wire        q1q2_xpipe_pipe_ch6_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch6_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch6_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch6_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch6_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch7_powerdown_m;
  wire        q1q2_xpipe_pipe_ch7_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch7_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch7_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch7_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch7_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch7_txdata_m;
  wire        q1q2_xpipe_pipe_ch7_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch7_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch7_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch7_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch7_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch7_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch7_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch7_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch7_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch7_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch7_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch7_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch7_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch7_rxdata_m;
  wire        q1q2_xpipe_pipe_ch7_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch7_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch7_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch7_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch7_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch8_powerdown_m;
  wire        q1q2_xpipe_pipe_ch8_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch8_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch8_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch8_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch8_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch8_txdata_m;
  wire        q1q2_xpipe_pipe_ch8_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch8_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch8_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch8_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch8_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch8_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch8_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch8_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch8_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch8_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch8_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch8_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch8_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch8_rxdata_m;
  wire        q1q2_xpipe_pipe_ch8_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch8_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch8_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch8_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch8_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch9_powerdown_m;
  wire        q1q2_xpipe_pipe_ch9_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch9_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch9_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch9_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch9_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch9_txdata_m;
  wire        q1q2_xpipe_pipe_ch9_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch9_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch9_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch9_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch9_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch9_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch9_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch9_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch9_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch9_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch9_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch9_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch9_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch9_rxdata_m;
  wire        q1q2_xpipe_pipe_ch9_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch9_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch9_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch9_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch9_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch10_powerdown_m;
  wire        q1q2_xpipe_pipe_ch10_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch10_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch10_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch10_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch10_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch10_txdata_m;
  wire        q1q2_xpipe_pipe_ch10_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch10_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch10_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch10_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch10_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch10_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch10_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch10_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch10_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch10_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch10_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch10_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch10_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch10_rxdata_m;
  wire        q1q2_xpipe_pipe_ch10_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch10_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch10_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch10_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch10_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch11_powerdown_m;
  wire        q1q2_xpipe_pipe_ch11_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch11_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch11_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch11_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch11_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch11_txdata_m;
  wire        q1q2_xpipe_pipe_ch11_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch11_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch11_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch11_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch11_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch11_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch11_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch11_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch11_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch11_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch11_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch11_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch11_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch11_rxdata_m;
  wire        q1q2_xpipe_pipe_ch11_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch11_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch11_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch11_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch11_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch12_powerdown_m;
  wire        q1q2_xpipe_pipe_ch12_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch12_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch12_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch12_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch12_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch12_txdata_m;
  wire        q1q2_xpipe_pipe_ch12_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch12_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch12_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch12_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch12_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch12_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch12_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch12_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch12_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch12_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch12_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch12_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch12_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch12_rxdata_m;
  wire        q1q2_xpipe_pipe_ch12_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch12_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch12_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch12_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch12_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch13_powerdown_m;
  wire        q1q2_xpipe_pipe_ch13_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch13_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch13_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch13_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch13_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch13_txdata_m;
  wire        q1q2_xpipe_pipe_ch13_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch13_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch13_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch13_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch13_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch13_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch13_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch13_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch13_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch13_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch13_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch13_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch13_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch13_rxdata_m;
  wire        q1q2_xpipe_pipe_ch13_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch13_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch13_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch13_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch13_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch14_powerdown_m;
  wire        q1q2_xpipe_pipe_ch14_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch14_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch14_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch14_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch14_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch14_txdata_m;
  wire        q1q2_xpipe_pipe_ch14_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch14_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch14_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch14_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch14_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch14_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch14_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch14_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch14_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch14_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch14_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch14_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch14_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch14_rxdata_m;
  wire        q1q2_xpipe_pipe_ch14_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch14_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch14_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch14_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch14_rxvalid_m;

  wire [1:0]  q1q2_xpipe_pipe_ch15_powerdown_m;
  wire        q1q2_xpipe_pipe_ch15_rxpolarity_m;
  wire        q1q2_xpipe_pipe_ch15_rxtermination_m;
  wire [1:0]  q1q2_xpipe_pipe_ch15_txcharisk_m;
  wire        q1q2_xpipe_pipe_ch15_txcompliance_m;
  wire        q1q2_xpipe_pipe_ch15_txdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch15_txdata_m;
  wire        q1q2_xpipe_pipe_ch15_txdeemph_m;
  wire        q1q2_xpipe_pipe_ch15_txdetectrxloopback_m;
  wire        q1q2_xpipe_pipe_ch15_txelecidle_m;
  wire [6:0]  q1q2_xpipe_pipe_ch15_txmaincursor_m;
  wire [2:0]  q1q2_xpipe_pipe_ch15_txmargin_m;
  wire [4:0]  q1q2_xpipe_pipe_ch15_txpostcursor_m;
  wire [4:0]  q1q2_xpipe_pipe_ch15_txprecursor_m;
  wire        q1q2_xpipe_pipe_ch15_txstartblock_m;
  wire        q1q2_xpipe_pipe_ch15_txswing_m;
  wire [1:0]  q1q2_xpipe_pipe_ch15_txsyncheader_m;
  wire        q1q2_xpipe_pipe_ch15_phystatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch15_rxcharisk_m;
  wire        q1q2_xpipe_pipe_ch15_rxdatavalid_m;
  wire [31:0] q1q2_xpipe_pipe_ch15_rxdata_m;
  wire        q1q2_xpipe_pipe_ch15_rxelecidle_m;
  wire        q1q2_xpipe_pipe_ch15_rxstartblock_m;
  wire [2:0]  q1q2_xpipe_pipe_ch15_rxstatus_m;
  wire [1:0]  q1q2_xpipe_pipe_ch15_rxsyncheader_m;
  wire        q1q2_xpipe_pipe_ch15_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch0_powerdown_m;
  wire        q2q3_xpipe_pipe_ch0_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch0_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch0_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch0_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch0_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch0_txdata_m;
  wire        q2q3_xpipe_pipe_ch0_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch0_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch0_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch0_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch0_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch0_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch0_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch0_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch0_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch0_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch0_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch0_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch0_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch0_rxdata_m;
  wire        q2q3_xpipe_pipe_ch0_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch0_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch0_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch0_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch0_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch1_powerdown_m;
  wire        q2q3_xpipe_pipe_ch1_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch1_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch1_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch1_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch1_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch1_txdata_m;
  wire        q2q3_xpipe_pipe_ch1_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch1_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch1_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch1_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch1_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch1_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch1_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch1_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch1_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch1_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch1_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch1_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch1_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch1_rxdata_m;
  wire        q2q3_xpipe_pipe_ch1_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch1_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch1_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch1_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch1_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch2_powerdown_m;
  wire        q2q3_xpipe_pipe_ch2_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch2_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch2_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch2_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch2_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch2_txdata_m;
  wire        q2q3_xpipe_pipe_ch2_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch2_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch2_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch2_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch2_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch2_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch2_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch2_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch2_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch2_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch2_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch2_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch2_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch2_rxdata_m;
  wire        q2q3_xpipe_pipe_ch2_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch2_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch2_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch2_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch2_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch3_powerdown_m;
  wire        q2q3_xpipe_pipe_ch3_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch3_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch3_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch3_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch3_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch3_txdata_m;
  wire        q2q3_xpipe_pipe_ch3_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch3_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch3_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch3_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch3_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch3_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch3_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch3_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch3_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch3_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch3_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch3_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch3_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch3_rxdata_m;
  wire        q2q3_xpipe_pipe_ch3_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch3_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch3_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch3_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch3_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch4_powerdown_m;
  wire        q2q3_xpipe_pipe_ch4_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch4_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch4_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch4_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch4_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch4_txdata_m;
  wire        q2q3_xpipe_pipe_ch4_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch4_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch4_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch4_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch4_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch4_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch4_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch4_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch4_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch4_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch4_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch4_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch4_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch4_rxdata_m;
  wire        q2q3_xpipe_pipe_ch4_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch4_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch4_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch4_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch4_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch5_powerdown_m;
  wire        q2q3_xpipe_pipe_ch5_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch5_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch5_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch5_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch5_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch5_txdata_m;
  wire        q2q3_xpipe_pipe_ch5_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch5_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch5_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch5_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch5_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch5_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch5_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch5_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch5_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch5_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch5_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch5_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch5_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch5_rxdata_m;
  wire        q2q3_xpipe_pipe_ch5_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch5_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch5_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch5_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch5_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch6_powerdown_m;
  wire        q2q3_xpipe_pipe_ch6_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch6_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch6_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch6_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch6_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch6_txdata_m;
  wire        q2q3_xpipe_pipe_ch6_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch6_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch6_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch6_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch6_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch6_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch6_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch6_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch6_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch6_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch6_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch6_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch6_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch6_rxdata_m;
  wire        q2q3_xpipe_pipe_ch6_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch6_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch6_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch6_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch6_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch7_powerdown_m;
  wire        q2q3_xpipe_pipe_ch7_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch7_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch7_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch7_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch7_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch7_txdata_m;
  wire        q2q3_xpipe_pipe_ch7_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch7_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch7_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch7_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch7_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch7_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch7_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch7_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch7_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch7_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch7_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch7_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch7_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch7_rxdata_m;
  wire        q2q3_xpipe_pipe_ch7_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch7_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch7_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch7_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch7_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch8_powerdown_m;
  wire        q2q3_xpipe_pipe_ch8_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch8_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch8_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch8_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch8_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch8_txdata_m;
  wire        q2q3_xpipe_pipe_ch8_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch8_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch8_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch8_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch8_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch8_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch8_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch8_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch8_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch8_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch8_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch8_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch8_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch8_rxdata_m;
  wire        q2q3_xpipe_pipe_ch8_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch8_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch8_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch8_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch8_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch9_powerdown_m;
  wire        q2q3_xpipe_pipe_ch9_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch9_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch9_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch9_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch9_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch9_txdata_m;
  wire        q2q3_xpipe_pipe_ch9_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch9_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch9_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch9_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch9_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch9_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch9_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch9_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch9_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch9_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch9_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch9_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch9_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch9_rxdata_m;
  wire        q2q3_xpipe_pipe_ch9_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch9_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch9_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch9_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch9_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch10_powerdown_m;
  wire        q2q3_xpipe_pipe_ch10_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch10_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch10_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch10_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch10_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch10_txdata_m;
  wire        q2q3_xpipe_pipe_ch10_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch10_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch10_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch10_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch10_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch10_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch10_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch10_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch10_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch10_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch10_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch10_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch10_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch10_rxdata_m;
  wire        q2q3_xpipe_pipe_ch10_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch10_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch10_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch10_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch10_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch11_powerdown_m;
  wire        q2q3_xpipe_pipe_ch11_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch11_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch11_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch11_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch11_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch11_txdata_m;
  wire        q2q3_xpipe_pipe_ch11_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch11_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch11_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch11_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch11_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch11_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch11_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch11_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch11_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch11_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch11_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch11_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch11_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch11_rxdata_m;
  wire        q2q3_xpipe_pipe_ch11_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch11_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch11_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch11_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch11_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch12_powerdown_m;
  wire        q2q3_xpipe_pipe_ch12_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch12_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch12_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch12_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch12_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch12_txdata_m;
  wire        q2q3_xpipe_pipe_ch12_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch12_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch12_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch12_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch12_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch12_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch12_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch12_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch12_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch12_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch12_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch12_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch12_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch12_rxdata_m;
  wire        q2q3_xpipe_pipe_ch12_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch12_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch12_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch12_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch12_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch13_powerdown_m;
  wire        q2q3_xpipe_pipe_ch13_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch13_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch13_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch13_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch13_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch13_txdata_m;
  wire        q2q3_xpipe_pipe_ch13_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch13_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch13_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch13_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch13_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch13_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch13_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch13_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch13_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch13_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch13_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch13_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch13_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch13_rxdata_m;
  wire        q2q3_xpipe_pipe_ch13_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch13_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch13_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch13_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch13_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch14_powerdown_m;
  wire        q2q3_xpipe_pipe_ch14_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch14_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch14_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch14_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch14_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch14_txdata_m;
  wire        q2q3_xpipe_pipe_ch14_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch14_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch14_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch14_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch14_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch14_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch14_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch14_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch14_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch14_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch14_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch14_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch14_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch14_rxdata_m;
  wire        q2q3_xpipe_pipe_ch14_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch14_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch14_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch14_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch14_rxvalid_m;

  wire [1:0]  q2q3_xpipe_pipe_ch15_powerdown_m;
  wire        q2q3_xpipe_pipe_ch15_rxpolarity_m;
  wire        q2q3_xpipe_pipe_ch15_rxtermination_m;
  wire [1:0]  q2q3_xpipe_pipe_ch15_txcharisk_m;
  wire        q2q3_xpipe_pipe_ch15_txcompliance_m;
  wire        q2q3_xpipe_pipe_ch15_txdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch15_txdata_m;
  wire        q2q3_xpipe_pipe_ch15_txdeemph_m;
  wire        q2q3_xpipe_pipe_ch15_txdetectrxloopback_m;
  wire        q2q3_xpipe_pipe_ch15_txelecidle_m;
  wire [6:0]  q2q3_xpipe_pipe_ch15_txmaincursor_m;
  wire [2:0]  q2q3_xpipe_pipe_ch15_txmargin_m;
  wire [4:0]  q2q3_xpipe_pipe_ch15_txpostcursor_m;
  wire [4:0]  q2q3_xpipe_pipe_ch15_txprecursor_m;
  wire        q2q3_xpipe_pipe_ch15_txstartblock_m;
  wire        q2q3_xpipe_pipe_ch15_txswing_m;
  wire [1:0]  q2q3_xpipe_pipe_ch15_txsyncheader_m;
  wire        q2q3_xpipe_pipe_ch15_phystatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch15_rxcharisk_m;
  wire        q2q3_xpipe_pipe_ch15_rxdatavalid_m;
  wire [31:0] q2q3_xpipe_pipe_ch15_rxdata_m;
  wire        q2q3_xpipe_pipe_ch15_rxelecidle_m;
  wire        q2q3_xpipe_pipe_ch15_rxstartblock_m;
  wire [2:0]  q2q3_xpipe_pipe_ch15_rxstatus_m;
  wire [1:0]  q2q3_xpipe_pipe_ch15_rxsyncheader_m;
  wire        q2q3_xpipe_pipe_ch15_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch0_powerdown_m;
  wire        q3q4_xpipe_pipe_ch0_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch0_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch0_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch0_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch0_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch0_txdata_m;
  wire        q3q4_xpipe_pipe_ch0_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch0_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch0_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch0_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch0_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch0_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch0_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch0_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch0_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch0_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch0_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch0_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch0_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch0_rxdata_m;
  wire        q3q4_xpipe_pipe_ch0_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch0_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch0_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch0_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch0_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch1_powerdown_m;
  wire        q3q4_xpipe_pipe_ch1_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch1_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch1_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch1_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch1_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch1_txdata_m;
  wire        q3q4_xpipe_pipe_ch1_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch1_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch1_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch1_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch1_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch1_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch1_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch1_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch1_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch1_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch1_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch1_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch1_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch1_rxdata_m;
  wire        q3q4_xpipe_pipe_ch1_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch1_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch1_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch1_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch1_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch2_powerdown_m;
  wire        q3q4_xpipe_pipe_ch2_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch2_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch2_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch2_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch2_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch2_txdata_m;
  wire        q3q4_xpipe_pipe_ch2_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch2_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch2_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch2_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch2_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch2_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch2_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch2_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch2_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch2_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch2_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch2_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch2_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch2_rxdata_m;
  wire        q3q4_xpipe_pipe_ch2_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch2_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch2_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch2_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch2_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch3_powerdown_m;
  wire        q3q4_xpipe_pipe_ch3_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch3_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch3_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch3_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch3_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch3_txdata_m;
  wire        q3q4_xpipe_pipe_ch3_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch3_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch3_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch3_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch3_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch3_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch3_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch3_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch3_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch3_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch3_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch3_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch3_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch3_rxdata_m;
  wire        q3q4_xpipe_pipe_ch3_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch3_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch3_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch3_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch3_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch4_powerdown_m;
  wire        q3q4_xpipe_pipe_ch4_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch4_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch4_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch4_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch4_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch4_txdata_m;
  wire        q3q4_xpipe_pipe_ch4_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch4_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch4_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch4_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch4_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch4_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch4_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch4_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch4_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch4_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch4_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch4_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch4_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch4_rxdata_m;
  wire        q3q4_xpipe_pipe_ch4_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch4_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch4_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch4_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch4_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch5_powerdown_m;
  wire        q3q4_xpipe_pipe_ch5_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch5_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch5_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch5_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch5_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch5_txdata_m;
  wire        q3q4_xpipe_pipe_ch5_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch5_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch5_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch5_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch5_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch5_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch5_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch5_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch5_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch5_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch5_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch5_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch5_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch5_rxdata_m;
  wire        q3q4_xpipe_pipe_ch5_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch5_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch5_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch5_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch5_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch6_powerdown_m;
  wire        q3q4_xpipe_pipe_ch6_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch6_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch6_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch6_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch6_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch6_txdata_m;
  wire        q3q4_xpipe_pipe_ch6_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch6_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch6_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch6_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch6_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch6_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch6_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch6_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch6_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch6_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch6_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch6_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch6_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch6_rxdata_m;
  wire        q3q4_xpipe_pipe_ch6_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch6_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch6_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch6_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch6_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch7_powerdown_m;
  wire        q3q4_xpipe_pipe_ch7_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch7_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch7_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch7_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch7_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch7_txdata_m;
  wire        q3q4_xpipe_pipe_ch7_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch7_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch7_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch7_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch7_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch7_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch7_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch7_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch7_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch7_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch7_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch7_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch7_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch7_rxdata_m;
  wire        q3q4_xpipe_pipe_ch7_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch7_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch7_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch7_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch7_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch8_powerdown_m;
  wire        q3q4_xpipe_pipe_ch8_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch8_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch8_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch8_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch8_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch8_txdata_m;
  wire        q3q4_xpipe_pipe_ch8_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch8_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch8_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch8_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch8_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch8_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch8_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch8_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch8_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch8_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch8_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch8_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch8_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch8_rxdata_m;
  wire        q3q4_xpipe_pipe_ch8_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch8_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch8_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch8_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch8_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch9_powerdown_m;
  wire        q3q4_xpipe_pipe_ch9_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch9_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch9_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch9_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch9_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch9_txdata_m;
  wire        q3q4_xpipe_pipe_ch9_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch9_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch9_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch9_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch9_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch9_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch9_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch9_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch9_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch9_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch9_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch9_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch9_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch9_rxdata_m;
  wire        q3q4_xpipe_pipe_ch9_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch9_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch9_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch9_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch9_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch10_powerdown_m;
  wire        q3q4_xpipe_pipe_ch10_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch10_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch10_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch10_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch10_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch10_txdata_m;
  wire        q3q4_xpipe_pipe_ch10_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch10_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch10_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch10_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch10_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch10_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch10_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch10_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch10_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch10_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch10_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch10_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch10_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch10_rxdata_m;
  wire        q3q4_xpipe_pipe_ch10_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch10_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch10_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch10_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch10_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch11_powerdown_m;
  wire        q3q4_xpipe_pipe_ch11_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch11_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch11_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch11_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch11_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch11_txdata_m;
  wire        q3q4_xpipe_pipe_ch11_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch11_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch11_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch11_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch11_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch11_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch11_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch11_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch11_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch11_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch11_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch11_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch11_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch11_rxdata_m;
  wire        q3q4_xpipe_pipe_ch11_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch11_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch11_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch11_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch11_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch12_powerdown_m;
  wire        q3q4_xpipe_pipe_ch12_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch12_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch12_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch12_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch12_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch12_txdata_m;
  wire        q3q4_xpipe_pipe_ch12_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch12_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch12_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch12_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch12_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch12_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch12_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch12_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch12_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch12_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch12_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch12_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch12_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch12_rxdata_m;
  wire        q3q4_xpipe_pipe_ch12_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch12_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch12_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch12_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch12_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch13_powerdown_m;
  wire        q3q4_xpipe_pipe_ch13_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch13_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch13_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch13_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch13_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch13_txdata_m;
  wire        q3q4_xpipe_pipe_ch13_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch13_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch13_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch13_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch13_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch13_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch13_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch13_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch13_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch13_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch13_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch13_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch13_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch13_rxdata_m;
  wire        q3q4_xpipe_pipe_ch13_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch13_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch13_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch13_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch13_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch14_powerdown_m;
  wire        q3q4_xpipe_pipe_ch14_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch14_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch14_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch14_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch14_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch14_txdata_m;
  wire        q3q4_xpipe_pipe_ch14_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch14_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch14_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch14_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch14_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch14_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch14_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch14_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch14_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch14_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch14_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch14_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch14_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch14_rxdata_m;
  wire        q3q4_xpipe_pipe_ch14_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch14_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch14_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch14_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch14_rxvalid_m;

  wire [1:0]  q3q4_xpipe_pipe_ch15_powerdown_m;
  wire        q3q4_xpipe_pipe_ch15_rxpolarity_m;
  wire        q3q4_xpipe_pipe_ch15_rxtermination_m;
  wire [1:0]  q3q4_xpipe_pipe_ch15_txcharisk_m;
  wire        q3q4_xpipe_pipe_ch15_txcompliance_m;
  wire        q3q4_xpipe_pipe_ch15_txdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch15_txdata_m;
  wire        q3q4_xpipe_pipe_ch15_txdeemph_m;
  wire        q3q4_xpipe_pipe_ch15_txdetectrxloopback_m;
  wire        q3q4_xpipe_pipe_ch15_txelecidle_m;
  wire [6:0]  q3q4_xpipe_pipe_ch15_txmaincursor_m;
  wire [2:0]  q3q4_xpipe_pipe_ch15_txmargin_m;
  wire [4:0]  q3q4_xpipe_pipe_ch15_txpostcursor_m;
  wire [4:0]  q3q4_xpipe_pipe_ch15_txprecursor_m;
  wire        q3q4_xpipe_pipe_ch15_txstartblock_m;
  wire        q3q4_xpipe_pipe_ch15_txswing_m;
  wire [1:0]  q3q4_xpipe_pipe_ch15_txsyncheader_m;
  wire        q3q4_xpipe_pipe_ch15_phystatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch15_rxcharisk_m;
  wire        q3q4_xpipe_pipe_ch15_rxdatavalid_m;
  wire [31:0] q3q4_xpipe_pipe_ch15_rxdata_m;
  wire        q3q4_xpipe_pipe_ch15_rxelecidle_m;
  wire        q3q4_xpipe_pipe_ch15_rxstartblock_m;
  wire [2:0]  q3q4_xpipe_pipe_ch15_rxstatus_m;
  wire [1:0]  q3q4_xpipe_pipe_ch15_rxsyncheader_m;
  wire        q3q4_xpipe_pipe_ch15_rxvalid_m;
